Document Reference No.: FT_000367
UM232H Single Channel USB Hi-Speed FT232H Development Module Error!
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Datasheet Version 1.3
Clearance No.: FTDI# 198
by SETUP (SetBitMode) command. Each Multi-Purpose UART/FIFO Controller also contains an MPSSE
(Multi-Protocol Synchronous Serial Engine). Using this MPSSE, the Multi-Purpose Serial/FIFO Controller can
be configured under software command, to have one of the MPSSE interfaces (SPI, I 2 C, and JTAG).
USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface
between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol
specification.
Port FIFO TX Buffer (1Kbytes). Data from the Host PC is stored in these buffers to be used by the Multi-
purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and FIFO control block.
Port FIFO RX Buffer (1Kbytes). Data from the Multi-purpose Serial/FIFO controllers is stored in these
blocks to be sent back to the Host PC when requested. This is controlled by the USB Protocol Engine and
FIFO control block.
RESET Generator – The integrated Reset Generator Cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT232H. RESET#
should be tied to VCCIO (+3.3V) if not being used.
Baud Rate Generators – The Baud Rate Generators provides a x16 or a x10 clock input to the UART’s
from a 120MHz reference clock and consists of a 14 bit prescaler and 4 register bits which provide fine
tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the
UART, which is programmable from 183 baud to 12 Mbaud. See FTDI application note AN_120 on the FTDI
website for more details.
EEPROM Interface . If the external EEPROM is fitted, the FT232H can be configured as an asynchronous
serial UART (default mode), parallel FIFO (245) mode, FT1248, fast serial (opto isolation) or CPU-Style
FIFO. The EEPROM should be a 16 bit wide configuration such as a 93LC56B or equivalent capable of a
1Mbit/s clock rate at VCCIO = +2.97V to 3.63V. The EEPROM is programmable in-circuit over USB using a
utility program called FT_Prog available from FTDI web site.
+1.8/3.3V LDO Regulator. The +3.3/+1.8V LDO regulator generates +1.8 volts for the core and the USB
transceiver cell and +3.3V for the IO and the internal PLL and USB PHY power supply.
UTMI PHY . The Universal Transceiver Macrocell Interface (UTMI) physical interface cell is the USB
transceiver. This block handles the Full speed / Hi-Speed SERDES (serialise – deserialise) function for the
USB TX/RX data. It also provides the clocks for the rest of the chip. A 12 MHz crystal must be connected to
the OSCI and OSCO pins or 12 MHz Oscillator must be connected to the OSCI, and the OSCO is left
unconnected. A 12K Ohm resistor should be connected between REF and GND on the PCB.
The UTMI PHY functions include:
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Su pports 480 Mbit/s “Hi - Speed” (HS)/ 12 Mbit/s “Full Speed” (FS).
SYNC/EOP generation and checking
Data and clock recovery from serial stream on the USB.
Bit-stuffing/unstuffing; bit stuff error detection.
Manages USB Resume, Wake Up and Suspend functions.
Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.
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? Copyright 2012 Future Technology Devices International Ltd
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